Although power consumption is known to increase due to leakage currents within insulating films for wiring layers, the impact of leakage on the device as a whole has been small in those generations of semiconductor devices where the spacing between adjacent wirings was more than 1 μm. However, at line spacings of 1 micron or less, the impact on power consumption is larger due to the narrower line spacings and the increase in the scale of the circuitry. In particular, as the semiconductor industry moves toward the production of circuitry at line spacings of 0.1 μm or less, leakage currents between wirings will have a large impact on the characteristics and life of the semiconductor device.
One method currently used to form the wiring in semiconductor devices is the damascene method which involves first etching an insulating film so as to form therein trenches in the shape of the wiring lines, then plating the trenches to form copper lines. However, in this damascene method, the etching inevitably incurs damage on the insulating film, resulting in increased leakage or a deterioration in the time-dependent dielectric breakdown (TDDB) properties, etc. owing to the roughness of the wiring trenches, which significantly lowers product yield and reliability during semiconductor manufacture.
In light of these circumstances, there is a need to either minimize damage to the insulating film when etching is carried out at the time of wiring trench formation or to carry out surface treatment so as to reduce leakage after etching has been carried out.
Surface treatments that are currently carried out to minimize etching damage include hydrophobization of the wiring trenches after etching, as disclosed in the respective claims of, for example, Japanese Patent Application Laid-open No. H6-267946, Japanese Patent Application (Published Japanese Translation of PCT International Publication) Nos. 2004-511896 and 2004-513503, Japanese Patent Application Laid-open No. 2004-292304 and Japanese Patent Application (Published Japanese Translation of PCT International Publication) No. 2007-508691.
However, with a method like that mentioned above, the requisite device characteristics are not obtained when reliability tests such as a TDDB test are carried out. It thus became apparent that increasing the reliability will require further improvements.